Search results

[LLHD][Deseq] Reset-only async reset process is not lowered to seq.firreg

Status: Open.

#10340 In llvm/circt;

· gipsyh opened on Apr 28, 2026

[Synth] Add NLDM attribute and enhance LibertyParser

Status: Open.

#10339 In llvm/circt;

· uenoku opened on Apr 28, 2026

[OM] Illegal to remove dead object

Status: Open.

#10332 In llvm/circt;

· uenoku opened on Apr 26, 2026

Feature Request: Native support for negedge clock in FIRRTL

Status: Open.

#10329 In llvm/circt;

· sequencer opened on Apr 26, 2026

[--flatten-memref] Flattened Indices are incorrect

Status: Open.

#10326 In llvm/circt;

· Abhilekhgautam opened on Apr 25, 2026

[FIRRTL] Dead port elimination on non-public module targeted by firrtl.simulation breaks verifier

FIRRTLInvolving the `firrtl` dialectInvolving the `firrtl` dialect

Status: Open.

#10317 In llvm/circt;

· fabianschuiki opened on Apr 24, 2026

[Synth][circt-synth] Allow transform dialect to specify user defined synthesis pipelines

enhancementNew feature or requestNew feature or request

Synth

Status: Open.

#10315 In llvm/circt;

· uenoku opened on Apr 24, 2026

[circt-verilog] Hang in llhd-mem2reg

bugSomething isn't workingSomething isn't working

ImportVerilog

Status: Open.

#10314 In llvm/circt;

· seldridge opened on Apr 24, 2026

[MSFT] Integration tests failure with -DLLVM_ENABLE_REVERSE_ITERATION=On

Status: Open.

#10299 In llvm/circt;

· uenoku opened on Apr 22, 2026

[AIGERImporter] Add lowering for justice and fairness properties

Status: Open.

#10298 In llvm/circt;

· okekayode opened on Apr 22, 2026

[FIRRTL] IMDeadCodeElim intermittent crash

bugSomething isn't workingSomething isn't working

FIRRTLInvolving the `firrtl` dialectInvolving the `firrtl` dialect

Status: Open.

#10274 In llvm/circt;

· seldridge opened on Apr 19, 2026

[ExportVerilog] Add ExportVerilogPipeline (Prettify, HWLegalizeModules, ExportVerilog) etc

Status: Open.

#10268 In llvm/circt;

· uenoku opened on Apr 18, 2026