Fix aarch64 page table parsing for 5 level paging (#158)

With 2511, the arm mmu library added support for an additional paging
level. When this occurs the current debugger logic will underflow and
start parsing the page tables with garbage levels and entry counts. This
change updates the level calculation to reflect the arm mmu library
changes.

Author: cfernald

DebuggerFeaturePkg/Library/DebugAgent/AARCH64/DebugAarch64.c

@@ -332,7 +332,7 @@ DebugArchInit (
 BOOLEAN
 ParsePageTableLevel (
   IN  UINT64  *TranslationTable,
-  IN  UINTN   TableLevel,
+  IN  INTN    TableLevel,
   IN  UINT64  *LastBlockEntry,
   IN  UINTN   Address,
   OUT UINTN   *Attributes
@@ -388,7 +388,7 @@ CheckPageAccess (
   )
 {
   UINT64   *TranslationTable;
-  UINTN    TableLevel;
+  INTN     TableLevel;
   UINTN    EntryCount;
   UINTN    T0SZ;
   BOOLEAN  Result;
@@ -405,8 +405,8 @@ CheckPageAccess (
   Attributes       = 0;
   TranslationTable = (UINT64 *)DebugGetTTBR0BaseAddress ();
   T0SZ             = DebugGetTCR () & TCR_T0SZ_MASK;
-  TableLevel       = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
-  EntryCount       = TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
+  TableLevel       = (T0SZ < MIN_T0SZ) ? -1 : (INTN)(T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
+  EntryCount       = TT_ENTRY_COUNT >> (INTN)(T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
 
   Result = ParsePageTableLevel (
              TranslationTable,